Metal-Oxide-Semiconductor (MOS) transistors find extensive use in modern integrated circuitry including chips fabricated with the standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. Depending on the operating conditions or modes of the integrated circuit, the substrate on which the transistors reside may require biasing. In those situations, the prior art teaches to apply a stable reference potential also referred to as DC bias to the substrate to control or enhance the operation of the integrated circuit and/or its transistors. In an integrated circuit, the substrate may be divided into regions that are doped differently. Each region is known as a well or tub, and may have one or more transistors. This is to provide electrical isolation between transistors in different wells. Each well of the substrate may be biased to a different potential.
In the simplest case, the prior art teaches to apply a single DC bias or potential to the substrate at all times. In other cases the prior art teaches selection of the DC potential depending on the change in operation modes or other parameters of the integrated circuitry. For example, U.S. Pat. No. 6,031,411 to Tsay et al. teaches a bias circuit to provide a stable substrate reference potential for a variety of operating modes. More specifically, Tsay uses a control circuit to select from among a plurality of substrate bias circuits only one substrate bias circuit to provide the substrate reference potential for a given operation mode. In U.S. Pat. No. 6,654,305 Tsunoda et al. teach to finely control power consumption of an Large Scale Integrated (LSI) system by using substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system. Tsunoda et al. use a substrate-bias control circuit for controlling the substrate-bias generation circuits. In addition, a storage unit is provided for storing control values to be supplied to the substrate-bias generation circuits. In U.S. Pat. No. 6,124,752 Kuroda teaches an integrated circuit that biases the semiconductor substrate to achieve power reduction in a stand-by mode based on threshold values. Still more methods and apparatus for controlling the substrate biases in accordance to operation modes of a processor are taught in U.S. Pat. No. 6,715,090 to Totsuka et al.
The above prior art references teach to apply one DC bias potential at a time to the substrate as a function of various performance parameters including operation mode and power consumption of an entire integrated circuit or of a large portion or module thereof. In U.S. Pat. No. 6,341,087 Kunikiyo teaches a semiconductor device with a body bias generation circuit that supplies a body region of an individual PMOS transistor with a body potential. The body potential is applied so that the body region may be reversely biased or not biased relative to the source region in response to an input signal.
Although the above prior art solutions are useful in many situations, new wireless voice and data communication systems capable of delivering megabits of data at a fast rate pose a new set of challenges. A focus of the integrated circuit industry is now on developing highly-integrated, low-cost and low-power circuits for processing radio-frequency (RF) analog signals at frequencies in excess of 1 GHz. In such circuits, low-noise amplifiers (LNAs) and power amplifiers (PAs) tend to be integrated on the same chip in the standard CMOS technology. To further increase the integration level, transmit-receive (T/R) switches must be integrated as well.
Unfortunately, performance parameters stand in the way of integrating T/R switches in CMOS circuits operating at high frequencies. Specifically, even with prior art substrate biasing solutions, MOS transistors in modern CMOS technology do not exhibit the linearity and loss performance at the desired frequencies to serve in T/R switches. In fact, the use of MOS transistors in CMOS technology for other low-loss and highly linear RF switches, e.g., RF switches for selecting capacitors for tuning frequency selective circuits such as voltage-controlled-oscillators (VCOs), is also compromised. Therefore, in the case of T/R switches for high-speed wireless applications, the prior art teaches the use of discrete components such as GaAs Field-Effect Transistors (MESFETs) and PIN-type diodes.
Another factor limiting the performance of RF integrated circuits is the substrate resistance of the MOS transistor. In common practice, the substrate resistance of a MOS transistor is minimized to prevent latch-up and improve breakdown voltage. This is achieved by surrounding the transistor with substrate contacts and strapping these with a low-resistance metal that is connected to a proper fixed voltage (such as ground). However, in certain RF transceiver blocks, e.g., LNAs, it is desirable to contemporaneously have as large a substrate resistance for the cascade transistor as possible. Of course, maximizing substrate resistance in these blocks compromises the latch-up immunity predicated on minimized substrate resistance. Furthermore, it is often difficult to increase the substrate resistance of a MOS transistor due to technology constraints.
Hence, what is desired is a MOS transistor with substrate impedance that can be adjusted to match the performance requirements.